10. CACHE Instructions
The CACHE instruction physical address, PA[Cachesize-2..Blocksize], defines the address and PA[0] defines the way to be invalidated.
The invalidation occurs in the following sequence:
1. The processor reads the STag, PIdx, and State bits from the secondary cache tag array. If State = 00 (Invalid) no further activity takes place. If there is a valid entry, then the STag is used to interrogate the primary instruction and data caches.
2. The processor reads each subset block from the primary instruction cache. If ITag = STag and IState = 1 (Valid) then the block is invalidated by writing the IState bit to 0 (Invalid) and the IState parity bit to 0.
3. Read each subset block from the primary data cache. If DTag = STag and DState is not equal to 00 (Invalid), then write the DState bits = 00 (Invalid), the StateMod bits = 001 (Normal), the SCWay bit = 0, and the DState parity bit = 0. If the original block is DState = 112 (Dirty) and StateMod = 0102 (Inconsistent), also write this block back to the secondary cache using the DTag and the SCWay bit from the primary data tag array.
4. Set the state of the secondary cache block to 00 (Invalid). Since the secondary cache is designed so all tag bits must be written at once, the Tag, VA, and ECC bits are also written. The tag is written with the PA and VA[13:12] (virtual index) of the original CACHE instruction address. The ECC is generated.
5. If the secondary cache block's original State bits were 112 (Dirty), the block is written back to the system interface unit. If the block's State was Shared or CleanExclusive the system interface unit is notified with a Tag Invalidation request that the block has been deleted.
The MRU bit is set to point away from the block invalidated unless the line was already invalid.
